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74LVT16952 * 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
January 2000 Revised October 2001
74LVT16952 * 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register. The LVTH16952 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The registered transceiver is designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16952 and LVTH16952 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16952) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 16952 s Latch-up conforms to JEDEC JED78 s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:
Order Number 74LVT16952MEA (Preliminary) 74LVT16952MTD (Preliminary) 74LVTH16952MEA 74LVTH16952MTD Package Number MS56A MTD56 MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2001 Fairchild Semiconductor Corporation
DS500103
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74LVT16952 * 74LVTH16952
Connection Diagram
Pin Descriptions
Pin Names A0-A16 B0-B16 CPABn, CPBAn CEAn, CEBn OEABn, OEBAn Description Data Register A Inputs B-Register 3-STATE Outputs Data Register B Inputs A-Register 3-STATE Outputs Clock Pulse Inputs Clock Enable Output Enable Inputs
Truth Table
(Note 1) Inputs An CPABn CEAn OEABn X X L L H H X X X X X H H L L L L X X X X L H L H L H L L H H Internal Register Output Value NC NC L L H H NC NC NC NC Bn B0 Z L Z H Z B0 B0 Z Z

L H L H
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = Output High Impedance = LOW-to-HIGH Transition. NC = No Change (state established by last valid CP) B0 = State established by last valid CP
Note 1: A to B data flow shown; B to A flow control is the same, but used OEBAn, CPBAn and CEBn.
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74LVT16952 * 74LVTH16952
Logic Diagram
Note: n for either byte 1 or byte 2. Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT16952 * 74LVTH16952
Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA
-32
64
-40
0
+85
10
C
ns/V
t/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed.
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74LVT16952 * 74LVTH16952
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 4) II(OD) (Note 4) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZL (Note 4) IOZH IOZH (Note 4) IOZH+ ICCH ICCL ICCZ ICCZ+ ICC 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 7)
Note 4: Applies to bushold version only (74LVTH16952). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
T A = -40C to +85C Min 2.0 0.8 VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 -5 5 5 10 0.19 5 0.19 0.19 0.2 Max -1.2
Units V V V V V V V V V V A A A A A A A A A A A A A A A mA mA mA mA mA
Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 3.0V VO = 0.0V VO = 0.5V VO = 3.6V VCC < V O 5.5V Outputs High Outputs Low Outputs Disabled VCC V O 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Bushold Input Minimum Drive
3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 8)
TA = 25C Units V V Conditions CL = 50 pF, RL = 500 (Note 9) (Note 9)
Min
Typ 0.8 -0.8
Max
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
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74LVT16952 * 74LVTH16952
AC Electrical Characteristics
TA = -40C to +85C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3 0.3V Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tW tS Maximum Clock Frequency Propagation Delay CPBA or CPAB to A or B Output Enable Time OE to A or B Output Disable Time OE to A or B Pulse Width, CPAB or CPBA HIGH or LOW Setup Time A or B before CPAB or CPBA CEA or CEB before CPAB or CPBA tH Hold Time A or B after CPAB or CPBA CEA or CEB after CPAB or CPBA tOSLH tOSHL Output to Output Skew (Note 10) 150 1.3 1.3 1.0 1.0 2.1 2.1 3.3 1.7 2.0 0.8 0.4 1.0 1.0 4.4 4.8 4.3 4.8 5.7 5.1 Max VCC = 2.7V Min 150 1.3 1.3 1.0 1.0 2.1 2.1 3.3 2.5 ns 2.8 0.0 ns 0.0 1.0 1.0 ns 4.7 5.0 4.9 5.7 6.2 5.3 Max MHz ns ns ns ns Units
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 11)
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VCC = OPEN, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT16952 * 74LVTH16952
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74LVT16952 * 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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